Semiconductor memory device having a transistor, a bit line, a word line and a stacked capacitor

US5714779A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Stephan Auer · Dachau, DE
• Armin Kohlhase · Neubiberg, DE
• Hanno Melzner · Sauerlach, DE

Key dates

• Filing date: Oct 11, 1996
• Grant date: Feb 3, 1998
• Expiry date: Oct 11, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A semiconductor memory configuration and a manufacturing process for the semiconductor memory configuration use a polishing process in the manufacture of a semiconductor memory configuration with stacked-capacitor-above-bit-line memory cells. At least TC pillars are created with the aid of a CMP step and a completely planarized surface existing prior to the manufacture of the bit line. Further CMP steps are advantageously used, inter alia, in the manufacture of a TB pillar of a bit line which is countersunk in a trench and of a lower capacitor plate, as well as to completely planarize a cell array and a periphery prior to interconnection of the circuit.