Apparatus and method of converting subtractive decode device cycles to positive peripheral component interface decode device cycles
US5715411A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 1996 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Jan 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for converting a subtractive device decode cycle to a peripheral component interface device decode cycle comprising a data communications bus (45), an interface (110) to the data communications bus (45), a function decoder (125) and device decoder (12) coupled to the interface (110). The function decoder (125) and device decoder (120) detect the presence of predetermined command and device types, respectively, on the data communications bus (45). The function decoder (125) and device decoder (120) feed a device select drive circuit (135) when the proper address and command types are detected. Device addresses in preselected ranges are pass-through and maintained internally in order to prevent the subtractive decode agent (90) from grabbing the bus cycle. Also, a positive decode cycle detection circuit (130) is operably coupled to the device select drive circuit (135) to detect the presence of positive decode cycles after the subtractive decode device select signal has been asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.