System for, and method of, processing in hardware commands received from software without polling of the hardware by the software
US5715437A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1994 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Nov 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU introduces software commands to a first limited capacity memory (e.g. FIFO), on an integrated circuit chip. Data (e.g. graphics) from a first portion of a second memory (off chip) is processed in accordance with such commands. A second portion (e.g. FIFO) of the second memory may also store commands normally passing from the CPU through the first memory. When the first memory becomes full, the commands may pass from the CPU through the second portion of the second memory (which may have a storage capacity considerably greater than that of the first memory) and then through the first memory. The commands may continue to flow in this auxiliary path until the second portion of the second memory becomes empty. A third memory of a limited capacity on the chip may pass the commands from the CPU to the first memory in the normal operation or to the second portion of the second memory when the first memory becomes full. The CPU may also pass commands to other peripheral equipment while a ready line is high. When low, the ready line prevents commands from passing to the peripheral equipment while the third memory is full. However, a command may pass from the third memory to the first …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.