Bi-directional co-processor interface
US5715439A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1996 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Dec 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/15127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A co-processor interface allows both a general processor and a relay ladder processor to make repeated calls to each other in the execution of subroutines. A register transfer instruction detected by the relay ladder processor triggers a suspension of the general processor. Return of control to the general processor is accomplished at the same time a register value is provided to the general processor that the general processor uses to reinitialize its program counter. For most single level transfers of control, a single transition instruction between the general processor to the relay ladder processor is sufficient to perform a call.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.