Arithmetic apparatus for carrying out viterbi decoding at a high speed
US5715470A · kind A · utility
39Cited by
6References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 27, 1993 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Sep 27, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arithmetic apparatus in which while data read out of a memory is shifted by means of a barrel shifter by a shift bit number designated by data standing for an output signal of an inverter, data standing for an output signal of the barrel shifter is inputted to a shift register to thereby perform Viterbi decoding at a high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.