Dram mapping for a digital video decompression processor
US5717461A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 1996 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Jul 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A random access memory of a digital video decompression processor is mapped to enable the reconstruction of successive video frames of pixel data represented by a compressed video bitstream. A FIFO buffer is provided in the RAM for the compressed video bitstream. A first luminance anchor frame buffer and a first chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a first anchor frame used to predict B-frames. A second luminance anchor frame buffer and second chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a second anchor frame used to predict the B-frames. A first B-frame luminance buffer is provided in the RAM and sized to store less than 100% of the amount of luminance data in a first B-frame field. A second B-frame luminance buffer is provided in the RAM and sized to store at least 100% of the amount of luminance data in a second B-frame field. A B-frame chrominance buffer is provided in the RAM to store at least 100% of the amount of chrominance data in a B-frame. The anchor frames and B-frames are read from the RAM to ena…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.