Random access memory with fast, compact sensing and selection architecture
US5717645A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1997 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Feb 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory (RAM) (10) is disclosed. A network of driver lines (28) extends over a number of core arrays (12a-12p) connecting a control bank 24 with column decode banks (26a and 26b), and the column decode banks (26a and 26b) with sense banks 46 within the core arrays (12a-12p). The driver lines 28 include predecode lines 30 and clock lines 32 for coupling predecode signals and clock signals from the control bank 24 to the column decode banks (26a and 26b). In addition, the driver lines 28 include column select lines 34 and sense driver lines 36 for coupling column select signals and sense amplifier enable signals from the column decode banks (26a and 26b) to the sense banks 46. The sense banks 46 include sense amplifiers 80 that are shared between array quadrants 42 by decoded transfer gate banks (70a and 70b). Advantageous placement of precharge circuits 82 and equalization circuits 86 provides a compact sense bank structure 46.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.