Row/column decoder circuits for a semiconductor memory device
US5717650A · kind A · utility
14Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1996 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Dec 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Row/column decoder circuits for a semiconductor memory device. Switching elements are used to separate a main power line from the row decoder circuit to block power from the main power line to the row decoder circuit when a word line is not driven. Therefore, the amount of standby current consumption can be reduced. Also, switching elements are used to separate a main power line from the column decoder circuit to block power from the main power line to the column decoder circuit when a bit line is not selected. Therefore, the amount of standby current consumption can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.