Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing
US5717700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1995 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Dec 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention relates to a method (150) of construction of a scannable integrated circuit. The method includes forming a plurality of flip-flops on an integrated circuit where each flip-flop includes a system data transfer gate and a scan data transfer gate, the gates receiving control signals from a controller (152). A clock signal is routed to the flip-flops (154). Preferably, the flip-flops are placed in a manner to optimize the operation of the integrated circuit when in a system mode. The flip-flops are then coupled into scan chains such that the integrated circuit may operate at a scan mode frequency that is equal to or greater than a system mode frequency (156, 158, 160). An alternative method includes forming a plurality of input lines, a plurality of output lines, and a plurality of scan data paths such that each input line starts a balanced scan chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.