Data/clock recovery circuit
US5717728A · kind A · utility
12Cited by
10References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1996 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Apr 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Problems associated with variations in pulse amplitude due to, for example, intersymbol interference, which can otherwise create problems in timing recovery circuits using the edges of the pulses are overcome by basing timing recovery on the center of the received pulses rather than the leading or trailing edges. Although jitter due to variations in pulse amplitude is not eliminated, timing recovery is improved because jitter due to variations in the center of the pulse are less than is jitter in the edges of the pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.