Cache coherency mechanism for multiprocessor computer systems
US5717898A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1995 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | May 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system which maintains cache coherency includes first and second microprocessors each having an associated cache memory storing lines of data. Each line of data has associated protocol bits that indicate a protocol state consistent with write-through, write-back, or write-once cache coherency policies that are selected via a protocol selection terminal for different system configurations. In one configuration, the output and external address terminals of the first microprocessor are coupled to the external and output address terminals, respectively, of the second microprocessor. This configuration enables each microprocessor to snoop memory cycles to main memory initiated by the other microprocessor so that it can be readily determined if a particular cache has the latest version of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.