Avalanche-enhanced CMOS transistor for EPROM/EEPROM and ESD-protection structures

US5719427A · kind A · utility

Assignee

• Pericom Semiconductor Corporation · US

Inventors

• Paul C. F. Tong · San Jose, US
• Chi-Hung Hui · Cupertino, US

Key dates

• Filing date: Jan 14, 1997
• Grant date: Feb 17, 1998
• Expiry date: Jan 14, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/611

Abstract

A non-volatile memory cell uses a p+ diffusion region spaced a lateral distance from the n+ drain of the n-channel programmable transistor. A diode between this p+ diffusion and the n+ drain has a low breakdown voltage because of the close spacing of the high-doping n+ and p+ diffusions. This diode generates electrons when avalanche breakdown occurs. The avalanche electrons are swept up into the programmable gate during programming. Since the avalanche electrons are generated by the diode rather than by the programmable transistor itself, programming efficiency no longer depends on the channel length and other parameters of the programmable transistor. The breakdown voltage of the diode is adjusted by varying the lateral spacing between the n+ drain and the p+ diffusion. Smaller lateral spacing enter avalanche breakdown at lower voltages and thus program the programmable transistor at a lower drain voltage. A drain voltage less than the power supply is possible with the diode, eliminating the need for a charge pump for the drain. A deep p-type implant under the n+ drain can also form the diode. The diode can be used for input-protection (ESD) devices.