Delay circuit compensating for variations in delay time
US5719514A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 1996 |
| Grant date | Feb 17, 1998 |
| Priority date | — |
| Expiry date | Mar 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable delay circuit is provided which automatically compensates for variations in delay time due to manufacturing variables. The construction is such that with variable delay gates (VD) of a reference delay time generation circuit (21), the delay time for one cycle of a designed reference clock signal (CK) is compensated using a phase comparison device (22) and a low pass filter (23). By arranging the reference delay time generation circuit (21) proximately to paths (121-124 and 141-144) which are weighted with the same variable delay gates (VD) as in the reference delay time generation circuit (21), the reference delay time generation circuit (21) and the paths (121-124 and 141-144) are given the same extent of variation. Hence variations in delay time can be compensated for using the same control signal CTR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.