Method and apparatus for performing timing analysis on a circuit design
US5719783A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1996 |
| Grant date | Feb 17, 1998 |
| Priority date | — |
| Expiry date | Feb 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for efficiently performing timing analysis on a circuit design. The present invention essentially provides a hybrid between a path enumeration algorithm and a critical path algorithm. As such, the present invention increases the number and degree of timing violations reported by a Critical Path Analysis (CPA) algorithm, while maintaining a performance advantage over a Path Enumeration (PE) algorithm. This is accomplished by providing a number of "pseudo" clocks to selected latches within the circuit design database, thereby tricking the CPA algorithm into reporting more timing violations than would otherwise be reported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.