Frame-synchronous reproducing circuit
US5719873A · kind A · utility
15Cited by
10References
15Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jul 7, 1995 |
| Grant date | Feb 17, 1998 |
| Priority date | — |
| Expiry date | Jul 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0608
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are compared with each other. If the both are coincident with each other, the BIC pattern determination circuit (24) applies a high-level signal to a JK flip-flop (26) via an OR circuit (48), whereby a high-level signal representing that frame synchronization has been settled is outputted from the JK flip-flop (26).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.