Scan test
US5719877A · kind A · utility
7Cited by
4References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1995 |
| Grant date | Feb 17, 1998 |
| Priority date | — |
| Expiry date | Aug 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing the performance of a combinational logic circuit is described. In contrast to a structural test which verifies the operation of the combinational logic circuitry, a performance test allows the performance of a combinational logic circuit to be tested by determining the accuracy of a set of outputs resulting from a change in input bits to the combinational logic circuit. Thus, it is possible to monitor more closely performance aspects, such as the maximum delay from input to output of a combination logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.