Digital/analog bit synchronizer
US5719908A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1995 |
| Grant date | Feb 17, 1998 |
| Priority date | — |
| Expiry date | Jul 19, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.