5 Volt tolerant 3.3 volt output buffer
US5721508A · kind A · utility
27Cited by
2References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 24, 1996 |
| Grant date | Feb 24, 1998 |
| Priority date | — |
| Expiry date | Jan 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/08142
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuit for preventing the improper functioning of a CMOS output buffer that may occur due to the fact that since the output buffer P-channel may be coupled between a supply voltage and an output pad. If the pad is driven higher than the supply voltage by an external source, current may be injected into the parasitic diodes of the source/drain of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.