Memory system ensuring coherency for memory buffers in a data communication system
US5721871A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1996 |
| Grant date | Feb 24, 1998 |
| Priority date | — |
| Expiry date | Feb 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system (3) for storing data messages communicated between a processor unit (13) and a communication module (11) comprises a memory array (4) having a plurality of memory buffers (B0-BM) for storing the data messages. First logic circuitry (28) generates a lock signal for a memory buffer which lock signal is valid when the processor trait (13) reads the first data word of the data message stored in the memory buffer whilst the memory buffer is not being accessed by the communication module (11). Module decode logic (22) coupled to receive the lock signal prevents the communication module (11) from writing a data message to a memory buffer when a valid lock signal has been generated for that memory buffer. The memory system (3) further comprises second logic circuitry (30) for providing a busy signal to the processor unit (13) when the processor unit reads the first data word from a memory buffer. The busy signal forms part of the first data word read from the memory buffer, and its logic state indicates whether or not the memory buffer is being written to by the communication module (11).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.