Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus
US5721882A · kind A · utility
17Cited by
16References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1997 |
| Grant date | Feb 24, 1998 |
| Priority date | — |
| Expiry date | Feb 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus which includes a state machine which tests the condition of the PCI bus, the condition of a target device on the bus, and then generates signal to accomplish the transfer which signals vary with the ability of the target device to transfer the data at particular rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.