Data transfer between integrated circuit timer channels
US5721889A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1995 |
| Grant date | Feb 24, 1998 |
| Priority date | — |
| Expiry date | Nov 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Referring to FIGS. 20-24, in one embodiment, data can be transferred from the data register of a top adjacent timer channel (e.g. 400 in FIG. 20) to the data register of the timer channel itself (401), and from the data register of the timer channel itself (401) to the data register of the bottom adjacent timer channel (402). By programming control register bits (e.g. DVB bits 425-426, DTC bits 423-424, and DTS bits 427-428 in FIG. 21) of selected timer channels (401) to perform these inter-channel data transfers, both stacks and FIFO structures can be formed and used. Stack and FIFO data storage structures can reduce the frequency of service required by the timer channels (400-402), and thus reduce the number of interrupts which must be responded to by a CPU (13 in FIG. 1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.