Clocked high voltage switch
US5723985A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1995 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Nov 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduced for reducing the gated breakdown voltage requirement to approximately 10V. This reduced gated breakdown voltage requirement is easily met by special layout methods applied to various transistors in the circuit. The basic layout methods include the terminating of the field implant region near the N+P junction to expose the N+ diffusion over the P substrate to increase the junction breakdown and the gated diode breakdown, and the use of short channel length to reduce the threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.