Semiconductor memory device
US5724366A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 1996 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Oct 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The drain electrode of an N type MOSFET (Q16) is connected to a power source potential (V.sub.CC) through a fuse element (F1) (route cut-off element), and the source electrode is connected to the drain electrode of an N type MOSFET (Q17), and the drain electrode of the N type MOSFET (Q16) is connected to the input of an inverter (G16), and is also connected to a resistance element (R1) connected to a grounding potential (V.sub.SS). Having this configuration, a semiconductor memory device incorporating a test mechanism is provided in order to test plural semiconductor memory devices by using a tester having a single data judging circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.