Interface for connecting a bus to a random access memory using a two wire link
US5724537A · kind A · utility
128Cited by
146References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 6, 1997 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Mar 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The interface utilizes a plurality of swing buffers, and has a control module for coordinating accesses thereto, which is connected to the address generator by a specialized two-wire interface. The address generator and the source of data are clocked asynchronously and at different clock rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.