LRU pointer updating in a controller for two-way set associative cache
US5724547A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1996 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Jun 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller tag random access memory (RAM) is configured into two ways, each way including tag and valid-bit storage for associatively searching a directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. There are two lines selected during a line fill to one of the ways. A least recently used (LRU) pointer selects which way to fill on a line fill cycle. The right way is selected for a line fill in response to right hit signal provided that the LRU pointer points to the right way. The LRU pointer is flipped to point to the left way upon the filling of the right line of the right way. The left way is selected for a line fill in response to a left hit signal provided that the LRU pointer points to the left way. The LRU pointer is flipped to point to the right way upon the filling of the left line of the left way.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.