Method for improving cache locality of a computer program
US5724586A · kind A · utility
11Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for improving the cache locality of an application executing in a computer system by decomposing the application into one or more threads and subsequently scheduling the execution of the threads such that a next thread to be executed is likely to reside in cache. The method operates by identifying a tour of points through a k-dimensional space such that cache misses are minimized. The space is divided into a plurality of equally sized blocks and may be extended for application to multiple cache levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.