Off-chip driver circuit with reduced hot-electron degradation
US5726589A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1995 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Nov 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output driver circuit for a semiconductor chip has a push-pull output with a P-channel pull-up and an N-channel pull-down. Predrivers produce push-pull outputs for driving the gates of the output driver. In previous circuits, a stacked arrangement was usually employed where the N-channel pull-down transistor had another N-channel transistor, with gate connected to the voltage supply, in series with it. In this invention, a parallel N-channel or P-channel transistor is employed to shunt part of the current at the beginning of a transition from high-to-low at the output node of the off-chip driver circuit, and thus lower the voltage across the pull-down transistor to a level which will avoid hot-electron degradation. This parallel transistor is small compared to the main N-channel pull-down, and serves to reduce the output node voltage to a level which does not present a likelihood of hot-electron effects in the main pull-down device. Thus, large current flow through the N-channel pull-down is delayed until the voltage is reduced to an acceptable level. At the same time, this delay is not such as would unduly compromise the high speed nature of the circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.