Phase locked loop using a counter and a microcontroller to produce VCXO control signals
US5726607A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1994 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Feb 4, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digitally controlled phase locked loop generates a derived clock signal that is frequency locked to a reference clock signal. The apparatus is comprised of a microcontroller, counter, digital to analog converter (DAC) and a voltage controlled crystal oscillator (VCXO) connected in a feedback loop arrangement. A frequency output derived from the VCXO periodically samples an incoming reference signal. The sampled count value is compared to an ideal count value associated with the same sampling time period. A microcontroller and software-based algorithm perform the phase comparison and loop filter operations of the phase locked loop (PLL).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.