Integral bit error rate test system for serial data communication links
US5726991A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 20, 1995 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Oct 20, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/241
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.