Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof
US5726994A · kind A · utility
9Cited by
8References
6Claims
0Family size
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Key dates
| Filing date | Feb 29, 1996 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Feb 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.