Apparatus and method for testing of integrated circuits
US5726997A · kind A · utility
Inventor
Key dates
| Filing date | May 22, 1995 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | May 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Current monitoring cells are located at selected locations on power supply lines within a chip. Each cell compares the current flow at predetermined times with a reference. If the current exceeds the reference, a signal is provided indicating a fault in the chip. A flip flop in the cell is set to maintain an indication of the fault condition. In two embodiments, the cells are connected with a scan chain which is used to sequentially access the test results for each cell. A third embodiment does not include the scan chain. A current divider may be included in each cell to isolate the voltage drop of the fault sensor from the functional circuit to minimize the impact of measuring the current for fault detection purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.