Phase locked loop using digital loop filter and digitally controlled oscillator
US5727038A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1996 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Sep 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (10) with a phase detector (11), a digital loop filter (12), a digital controlled oscillator (13) and a divide-by-N circuit (14) generates a periodic signal which has a predetermined phase and voltage related to a reference clock signal. A phase and frequency detector (21) outputs an average of error between a feedback delay clock and a reference clock to the digital loop filter (12). The digital loop filter (12) processes the phase detector (11) output and the inband quantization noise utilizing a sigma delta converter. The digital loop filter (12) utilizes a non binary weight scheme to minimize the number of bits changing states. The digital controlled oscillator (13) generates a loop clock signal utilizing a plurality of digital programmable delay elements. A divide-by-N circuit (14) performs a divide by 2560.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.