Memory including master and local word lines coupled to memory cells storing access information
US5727180A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/least recently used (LRU) cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. The master word lines and local word lines having approximately the same cycle time. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The architecture circuitry efficiently updates the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.