Signal processor
US5727216A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1995 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Jul 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03G2215/00599
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A signal processor having excellent noise resistance characteristics while maintaining superior synchronizing characteristics for hardware interrupt processes. Signal A output from a port REM of a high order CPU is input in parallel as signals B and C to an interrupt port INT of a motor drive control CPU, and to a normal input port Pi, respectively. Timers x and y are started at the same time as interrupt signal B falls, timer y counts up to time Y before time X set by timer x, and at that time a determination is made as to whether or not signal C input to port Pi and signal B input to port INT are identical. If signals B and C are identical, they are normal input signals, and pulse signals are output from ports P0-P3 after time X elapses. If signals B and C are different, a pulse signal is not output from the ports P0-P3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.