Method for planarizing a semiconductor layer
US5728507A · kind A · utility
8Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1996 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | Feb 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A moat pattern (19) is formed in a first layer of material (11) to improve the profile of a planarization process. The presence of the moat pattern (19) in the periphery of a semiconductor substrate (10,30) moves the effects of the relaxation distance (13) away from the critical areas of the semiconductor substrate (30). The moat pattern (19) is formed during a photolithographic process by using a photolithographic mask (20) that has a portion (22) that defines and patterns the moat pattern (19). The moat pattern (19) is defined as edge dice (31) are patterned across the semiconductor substrate (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.