Linear differential gain stage
US5729176A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1996 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | May 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/3211
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A linear differential gain stage (31) has a first input (32), a second input (33), a first output (34), and a second output (35). A differential input voltage is coupled to an input differential transistor pair (39,40). Voltage compensation circuits (53,54) cancel non-linearities due to the input differential transistor pair (39,40). Parasitic capacitance of the input differential transistor pair (39,40) couple current to the first and second inputs (32,33) due to voltage transitions at the first and second outputs (34,35). The current to the first and second inputs (32,33) is canceled by impedance compensation circuits (55,56) that provide an equal magnitude but opposite sign current. The result is an almost infinite input impedance to the linear differential gain stage (31).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.