Variable Frequency Divider
US5729179A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Sep 26, 1996 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | Sep 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a variable frequency divider capable of N+1/2 frequency division, a programmable frequency divider alternately frequency-divides an input signal by a frequency division ratio N (N being an integer) or by a frequency division ratio N+1. A first signal generating circuit generates a first signal in synchronism with an output signal of the programmable frequency division circuit. A second signal generating circuit generates a second signal which is identical to the first signal but delayed by half a period of the input signal. An output circuit alternately selects the first and second signals, and outputs the selected signal as frequency-divided signal. A delay circuit outputs a delayed signal identical to the first signal but delayed by one period of the input signal. A preset signal generating circuit alternately selects the delayed signal and the first signal, and presets the programmable frequency division circuit with the selected signal. The programmable frequency divider used may operate at the same speed as in N frequency division.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.