Single channel FIR filter architecture to perform combined/parallel filtering of multiple (quadrature) signals
US5729574A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1996 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | Oct 8, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reduced hardware complexity, reduced computational intensity finite impulse response filter architecture for filtering multiple (quadrature) channels of an RF modem comprises a cascaded arrangement of L data register stages through which respective digitally encoded data sample values of a signal to be filtered are sequentially clocked. Each data register stage has a data capacity greater than twice the code width of a respective digitized channel sample, so that each register stage can store both I and Q channel data. A multiplier unit is coupled to the data register and multiplies both I and Q contents of respective ones of the register stages by respective impulse response coefficient values. The resulting I and Q products are summed into I and Q channel convolutional sums.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.