Bus monitor system
US5729678A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1996 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | Mar 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus monitor system comprises eight identical programmable monitor circuits that are each connected to a monitored bus and to a local 16-bit event bus. There are three interfaces to the event bus within each monitor circuit. One interface asserts a predetermined bit pattern on the event bus when match conditions occur between bit patterns on the monitored bus and predetermined bit patterns stored in monitor circuit registers. A second interface asserts a signal on an external pin when bit patterns on the event bus match a predetermined bit pattern stored in a monitor circuit register. A third interface asserts a predetermined bit pattern on the event bus when an external device has asserted a signal on an external pin. Each monitor circuit is capable of reading and asserting any of the bits of the event bus. The event bus is used to enable or disable monitor circuit interfaces. If any asserted bit on the event bus matches a corresponding bit of one of the predetermined bit patterns stored in the interface enable and disable registers, that interface will be enabled or disabled, respectively. The event bus gives the monitor system the ability to simultaneously monitor for multiple …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.