Data driven information processing system using address translation table to keep coherent cache and main memories and permitting parallel readings and writings
US5729711A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 1994 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | May 31, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The system includes a data driven processor, a main memory, a cache memory and a memory access unit for accessing the cache memory, the main memory or both and for maintaining the contents of the cache memory in coherence with the contents of the main memory. Read/write from and to the memory can be carried out accurately at high speed without increasing the circuit scale. The memory access unit stores, in response to a write instruction, the data also in the cache memory. Even in a specific processing in which one data is read only once, the data can be read from the cache memory unit. Preferably, the memory access unit stores information specifying an access mode of the most recent access to the cache memory address by address, and compares the most recent access mode and the mode of the access to be taken. The memory access unit permits or inhibits access based on the result of comparison. A data item is not likely to be erroneously overwritten by the subsequent data before it is read. Preferably, the system includes main memories to which different addresses are allotted. The memory access unit accesses the cache memory by converting the address such that areas of different mai…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.