Timebase synchronization in separate integrated circuits or separate modules
US5729721A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1995 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | Nov 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Timebase channels in different I/O control modules (IOCMs 281-284 in FIG. 16) or on different integrated circuits (300-302 in FIG. 17 ) may provide synchronized, coherent timebase values to different blocks of work and other channels (e.g. 86 in FIG. 2) that are coupled to different timer buses (e.g. 71 in FIG. 2). In one embodiment, referring to FIGS. 1-19, two or more timebase channels, e.g. master timebase channel (285) and slave timebase channel (288), can be synchronized and kept in synchronization using just two signals, namely a clock signal (328) and a synchronization signal (329). The master timebase channel (285) generates or receives a master dock signal (328) which is coupled to one or more slave timebase channels (288) to ensure that the master and slave timebase channels (285, 288) increment or decrement at the same time and rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.