Isolation method in a semiconductor device
US5731221A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 1997 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Jan 10, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an isolation method in a semiconductor device. The method includes the steps of: forming a pad oxide film, a buffer polysilicon layer, and a nitride layer in that order on a semiconductor substrate where cell region and peripheral region having respective device isolation regions are defined; etching the nitride layer and the buffer polysilicon layer on the device isolation regions of the cell region and the peripheral region; forming a field oxide layer on the device isolation regions of the cell region and the peripheral region; etching the field oxide layer except for edge portions to expose the substrate in the device isolation regions of the cell region and the peripheral region; forming a first insulating layer on the substrate resulting from the previous etching step; etching the first insulating layer, to form a spacer in the side wall of the field oxide layer on the exposed substrate; etching the exposed substrate to form a trench; forming a second insulating layer on the substrate where the trench is formed, to fill the trench with the second insulating layer; etching the second insulating layer to planarize the surface of the substrate; an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.