Method of producing an EPROM with a trench insulating layer
US5731237A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Jan 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An EPROM allowing a miniaturization of an isolation region (a field insulating layer) without generating a parasitic transistor. The EPROM comprises a semiconductor substrate; a field insulating layer defining a device formation region of the semiconductor substrate; a gate insulating layer; a floating gate formed on the field insulating layer and the field insulating layer; a trench insulating layer extending into the semiconductor substrate at the center portion of the field insulating layer, one of the side walls of the trench insulating layer being self-aligned with the end face of the floating gate; a first interlaminar insulating layer covering the floating gate; a control gate located above the floating gate; a second interlaminar insulating layer formed over the whole surface; and a bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.