Programmable gate array for relay ladder logic
US5731712A · kind A · utility
Inventor
Key dates
| Filing date | Nov 9, 1995 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Nov 9, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/15057
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture is provided for field programmable gate army (FPGA) devices which implement relay ladder logic in PLC systems. Once the device is programmed, the implemented logic is executed in rung parallel fashion at electronic speeds. A direct correspondence of these devices in detail to relay ladder logic assures that technology mapping software for the FPGA device will run sufficiently fast for use in PLC systems. A reversible device programming method is required, so that the device can be reprogrammed conveniently to different relay ladder models. The architecture scales to families of devices of differing sizes and resources. A basic relay ladder logic is implemented, which supports various relay ladder logic dialects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.