Evaluation and amplifier circuit
US5731718A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An evaluation and amplifier circuit of the type of a keyed flipflop including at least two first transistors of a given channel type connected in series to each other disposed between first and second signal lines, has a connection from the gates of the first transistors to a respective one of the second and first signal lines. The first two transistors respectively form a first node common to the first two transistors for receiving a first control signal. A series circuit has at least two second transistors of the same channel type as the first transistors being connected in parallel to the first transistors, The gates of the first transistors are further connected with a respective one of the second and first signal lines. Furthermore, the amplifier circuit includes the feature that the second transistors form a second node common to the second transistors for receiving a second control signal, and a differential signal appearing on the signal lines is evaluated and amplified by the second transistors after the first transistors have received the differential signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.