Zero power fuse circuit
US5731734A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Oct 7, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356182
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A zero power fuse circuit includes a latch means having two inputs, a first input being latched to ground and a second input being latched to V.sub.cc. The latch means is triggered either by a momentary contact of the first input to ground or by the momentary contact of the second input to V.sub.cc. A first embodiment includes two fuse element/capacitor pairs each coupled to one of the two inputs of the latch means. A second embodiment includes a pull-up transistor and a fuse element/capacitor pair, coupled to the first and second inputs respectively. A third embodiment includes a pull-down transistor and a fuse element/capacitor pair respectively coupled to the second and first inputs of the latch means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.