Converter circuit arrangement with minimal snubber
US5731967A · kind A · utility
6Cited by
2References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 26, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Jun 26, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A converter circuit arrangement in which the gate turn-off thyristors are driven hard, i.e., the GTO is driven with a gate current configured in such a way that the turn-off gain IS/IGpeak is distinctly less than 3 so as to result in an anode voltage rise of at least 1 kV/.mu.s. The snubber circuit of such driven thyristors may be designed to include only a small number of elements. The voltage rise limiter includes at least one capacitor connected in parallel with one of the reverse-connected parallel diodes. The current rise limiter includes a parallel circuit having an inductor and a current limiting diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.