Single-precision, floating-point register array for floating-point units performing double-precision operations by emulation
US5732005A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1995 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Feb 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-precision floating-point register array for a floating-point execution unit that performs double-precision operations by emulation is provided. The register array comprises a plurality of single-precision floating-point registers and a storage device that stores one or more status bits in association with each of the plurality of registers; the status bits associated with each register indicate either that the associated data register contains single-precision or integer data, or that the data for the associated register is contained in an emulated register in memory that is mapped to the associated register. When a register is a source for an operation, the status bits associated with the register are checked and the required operand data for that register is read from the register or from an emulated register mapped to that register, as a function of the state of the status bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.