Output interfacing device programmable among three states for a memory in CMOS technology
US5732025A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Jun 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-state output interfacing device for a CMOS memory that comprises a stage for selective control of the device, receiving an input signal (I) at the bit frequency and a control signal (e) and making it possible to deliver, on two ports (A) and (B), either complemented signals (I), or distinct logic levels for driving the device into the high-impedance state, a first inverter stage delivering first inverted logic signals, from the ports (A) and (B), on two ports (C) and (D), a second inverter stage delivering second inverted signals from the ports (C) and (D), a stage for reducing the analog difference between the second inverted signals and for switching the output interfacing device into high-impedance state at ports (E) and (F), and an output stage receiving the signals from the ports (E) and (F) after reduction of analog difference and making it possible to fix and balance the current for charging and discharging the output capacitance of the output interfacing device and its high-impedance switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.