Bit error measurement circuit
US5732089A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Sep 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/203
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bit error measurement circuit is designed to measure a number of bit errors by comparing receiving data with a reference Pseudo-Noise pattern. Herein, a certain PN pattern is used as the receiving data in order to perform testing in performance of communications and transmission by evaluating the receiving data. There are provided multiple kinds of PN patterns each having a specific PN-stage number. The bit error measurement circuit is capable of automatically detecting a PN-stage number with respect to the receiving data. One method to do so is to perform comparison between the receiving data and an arbitrary pattern at timings which are periodically set to correspond to all PN-stage numbers each having a probability to be related to the receiving data, wherein the arbitrary pattern is extracted from the receiving data. Thus, the PN-stage number is automatically detected in response to the timing at which the receiving data coincide with the arbitrary pattern. Another method is to extract consecutive-0s patterns and consecutive-1s patterns from the receiving data and to perform comparison between a count value, corresponding to a number of bits of a longest consecutive-0s patter…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.